1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a semiconductor chip mounted on a flexible tape.
2. Description of the Related Art
In recent years, semiconductor devices (semiconductor packages) tend to have more pins and to have components mounted at higher density in order to meet requirements for smaller sizes and higher performance for electronic devices. As a result, the leads extending from semiconductor packages are spaced at smaller pitches, which make it difficult to install semiconductor packages on boards by gang reflow soldering. For this reason, more surface-grid-terminal-mounted semiconductor devices such as BGAs (Ball Grid Arrays) which are mounted by conductive protrusions such as solder balls on lower surfaces are employed in the art than peripheral-lead-mounted semiconductor devices such as QFP (Quad Flat Packages) which are mounted by leads on peripheral edges because the former semiconductor devices can have increased pitches.
Heretofore, semiconductor chips in semiconductor devices and leads thereof are mostly electrically connected by wire bonding. However, recent trends toward more pins on semiconductor devices result in reduced pitches between terminals (pads) on semiconductor chips, which make it difficult to connect the terminals and leads to each other by wire bonding. In view of the difficulty, attention has been directed to TAB (Tape Automated Bonding) as a substitute for wire bonding. TAB is a process of bonding inner leads mounted on a flexible insulating tape and having ends extending to a position for contact with terminals on a semiconductor chip, to bumps on the terminals on the semiconductor chip. According to TAB, it is possible to reduce the pitch of chip terminals to about 60 xcexcm. Surface-grid-terminal-mounted semiconductor devices installed on TAB are referred to as Tape-BGAs.
For fabricating conventional Tape-BGA semiconductor devices, attachment holes (device holes) are defined in regions of an insulating tape where semiconductor chips are positioned. Specifically a semiconductor chip is positioned in a device hole in an insulating tape, and is supported only by inner leads that are connected to terminals of the semiconductor chip.
Since all the weight of the semiconductor chip is borne by the inner leads, the inner leads need to have a high mechanical strength in the Tape-BGA semiconductor device. Before the semiconductor chip is installed on the insulating tape, it is necessary to exercise care in handling the insulating tape not to damage or deform the inner leads because part of the inner leads project into the device hole.
All electric interconnections are required to be disposed on the insulating tape around the device hole because the device hole is an area that cannot be used for electric interconnections and mounting. Since a space is needed on the insulating tape for accommodating a number of electric interconnections therein, there is a certain limitation to attempts to reduce the size of the insulating tape. Such electric interconnections have to be long enough to extend from the inner leads to conductive protrusions (solder balls) and thin enough to accommodate more pins, and are required to have a complex layout. However, long electric interconnections adversely affect electric characteristics of the semiconductor device, e.g., an increased impedance.
Usually, semiconductor devices of the type described above have electric interconnections classified into three groups, i.e., power supply interconnections, ground interconnections, and signal interconnections. All the electric interconnections of these three types extend on the insulating tape. Those electric interconnections which are connected to conductive protrusions (solder balls) that are positioned remotely from terminals (pads) of the semiconductor chip are long and hence have a high inductance, tending to cause a level of noise that cannot be ignored. Moreover, since different electric interconnections are connected respectively to all the terminals, the number of pins used is large, and the electric interconnections are arranged in a complex pattern.
Japanese laid-open patent publication No. 125721/1998 discloses an insulating tape which does not have attachment holes (device holes). The disclosed insulating tape has through holes defined at positions facing the terminals of a semiconductor chip. The semiconductor chip is mounted on the insulating tape by through hole bonding, and the terminals thereof are connected to electric interconnections on the reverse side of the insulating tape via the through holes. Though the insulating tape has no attachment holes (device holes), the insulating tape suffers a significant disadvantage in the semiconductor device fabrication process because it is highly complex and time-consuming to perform through hole bonding. Specifically, the process of producing through holes is complicated because it is necessary to define minute through holes in the insulating tape, form interconnections in the through holes, and fill the through holes with a synthetic resin, if necessary. In addition, the process of installing the semiconductor chip on the insulating tape is also highly complex and time-consuming because the semiconductor chip needs to be positioned highly accurately with respect to the through holes and then bonded in position. Accordingly, the through hole bonding technique is liable to make the semiconductor device fabrication process very complicated.
It is therefore an object of the present invention to provide a semiconductor device which requires no device hole, can be reduced in size, have short electric interconnections and stable electric characteristics, and can be fabricated by a relatively simple fabrication process.
According to the present invention, a semiconductor device includes a flexible insulating tape, a semiconductor chip mounted on a face side of the insulating tape by flip-chip bonding, a plane layer disposed in a region of the face side of the insulating tape substantially directly beneath the semiconductor chip, a plurality of filamentary interconnection patterns disposed in a region of the face side of the insulating tape substantially around the semiconductor chip, and a plurality of conductive protrusions disposed in respective openings defined in the insulating tape. The plane layer is held in contact with selected ones of a plurality of terminals of the semiconductor chip. The interconnection patterns are electrically independent of the plane layer and held in contact with remaining ones of the terminals of the semiconductor chip. The conductive protrusions are held in contact with the plane layer and selected ones of the interconnection patterns, and exposed on a reverse side of the insulating tape
With the above arrangement, since the semiconductor device has the plane layer to which a plurality of terminals are connected, the number of fine filamentary interconnection patterns is reduced, the layout thereof is made less complex, and the arrangement thereof is simplified. Furthermore, since the region directly beneath semiconductor chip is effectively utilized for electric interconnections, the semiconductor device may be reduced in size. Because the length of interconnections from the terminals through the plane layer to the conductive protrusions is small, the impedance thereof is small and the electric characteristics thereof are improved, allowing semiconductor chip to exhibit its own performance.
The process of fabricating the semiconductor device is highly simple because the semiconductor chip can be mounted on the insulating tape by simple flip-chip bonding without the need for a special complex process such as through hole bonding. Moreover, the conductive layer such as the plane layer and the interconnection patterns needs to be formed only on the face side (upper surface) of the insulating tape, and hence a board with interconnections on both surfaces thereof does not need to be used.
The plane layer may provide power supply interconnections, and the interconnection patterns may provide ground interconnections and signal interconnections. Alternatively, the plane layer may provide ground interconnections, and the interconnection patterns may provide power supply interconnections and signal interconnections.
If some of terminals are disposed in the vicinity of the center of the semiconductor chip, then the density of terminals and ends of interconnection patterns on outer peripheral edges of the semiconductor chip is lowered, allowing these terminals and interconnection patterns to be arranged in an easy layout. With the terminals in the vicinity of the center of the semiconductor chip being held in direct contact with the plane layer, no leads are required, the length of the interconnections is reduced, and the impedance thereof is lowered.
The plane layer may provide power supply interconnections and ground interconnections independent of each other, and the interconnection patterns may provide signal interconnections. With this arrangement, the density of terminals and ends of interconnection patterns on outer peripheral edges of the semiconductor chip is lowered, allowing these terminals and interconnection patterns to be arranged in an easy layout. Since a space needed for the interconnection patterns to extend therein is reduced, the semiconductor device can be further reduced in size. The lengths of both the ground interconnections and the power supply interconnections are small and their impedance is low as terminals thereof are held in direct contact with the plane layer without leads.
The semiconductor device may further include a floating plane layer disposed on the reverse side of the insulating tape and electrically insulated from the conductive protrusions. When a current flows through the plane layer and the interconnection patterns, an induced current is generated in the floating plane layer that is electrically independent. The induced current reduces the inductance of the plane layer and the interconnection patterns, and reduces the impedance thereof.
The conductive protrusions may comprise solder balls.
The semiconductor device may further include a support ring disposed on the face side of the insulating tape in surrounding relation to the semiconductor chip. The semiconductor chip and the support ring may have respective upper surfaces lying substantially flush with each other, and the semiconductor device may further include a heat spreader fixedly mounted on the upper surface of the semiconductor chip and the upper surface of the support ring. The support ring and the heat spreader act as reinforcing members to prevent the insulating tape from being easily deformed. Therefore, the conductive protrusions have their height and position maintained with high accuracy, and their defective ratio is held to a low value.